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Summary: Through analyzing the systematic bus AHB time sequence and static behavior on high speed one of 920T nuclear ARM processor store the controller SMC interface model, research IBM PC/ AT and IEEE PC/ 104 bus norm, puts forward a kind of scheme of realizing compatible PC/ 104 bus on ARM platform. Canvass the enormous difference in such aspects as memory structure, instruction system and bus time sequence between two kinds of platform systems thoroughly, provide and overcome these differences and methods to realize buses with compatible function. It is unable to use standard PC/ 104 templates of difficult problems that this compatible bus has been solved on ARM platform, it helps in the design of the embedded system and concurrently fetches ARM processor and advantage of PC/ AT system to adopt this scheme.
Foreword
PC/ 104 is a kind of industrial control bus norm specially defined for embedded application. Personal computer and ancillary equipment based on IBM PC/ AT bus norm have made the enormous achievement in employing, IEEE 1996 calls it ISA (industrial standard framework: Industry Standard Architecture) Bus. PC/ 104 is the extension of ISA standard, defines in IEEE-P996. In 1, are called the compatible PC embedded module standard. PC/ 104 is actually a kind of compact ISA, its definition of signal and Pc/ AT are basically identical, but electric and mechanical norms are totally different, it is the embedded bus systems of a kind of optimization, small-scale, heap structure. PC/ 104 bus comes from and practises the needing of development, benefits from the rapid development of PC technology at the same time, because development environment its friendly compatible chip abundant supporting advantaging such as being extensive by standard, engaged in the welcoming of embedded products manufacturer and system integration trader numerous, though ISA apparatus has been already uncommon now, PC/ 104 is still the current standard in the embedded systematic field.
ARM is the hot technology in the present embedded system employs. Because remarkable performance, lower price and extensive support of the semi-conductive manufacturer in the industry of ARM processor, there is extensive application in the embedded environment. ARM Company has created CHIPLESS mode, this company, through authorizing the high-efficient ARM kernel to the semi-conductive company, added to various peripheral function circuit and forms an intact chip according to the real application situation by the semi-conductive company, this kind of mode makes the semi-conductive manufacturer have the ability to produce various powerful specialized processor chips. AR M pays the utmost attention to using the single chip that may integrate the peripheral apparatus to every concrete application to the greatest extent because of SoC thought in the design, but expand the respect on the board very much and still lack the new industrial standard that can be accepted extensively.
1 PC/ AT model and PC/ 104 bus
1. A bus signal
PC/ 104_ 4 ] is a kind of 16 buses, but 8 compatible XT modes forward, the typical bus clock is 8 MHz, 4 clock pulses can finish intact bus once to visit, can insert a extra waiting for cycle in order to adapt to the low-speed peripheral hardware if necessary. The daily following signals in the embedded system develops.
1. 1. An address and data signal line
BALE bus address can enable the line of signal to latch, is driven by the platform CPU. When ISA expands card or DMA controller to take up buses, it is put as the logic 1 too.
SA~19: O> : Low 2O root address signal thread, are driven by having the persons who use of present bus.
LAd 23: 17> : Latch the signal line of address, the address space of memory used for visiting 16MB. Driven by the present bus owner or DMA controller.
SD <15:0> : .
1. 1. 2 bus cycle control signal lines
MEMR#: Store and read the line of signal.
MEMW #: Write the line of signal with memory.
IOR#: I/ O I/ O reads the line of signal.
IOW #: I/ O I/ O writes the line of signal.
1. 1. 3 cut off and DMA (Direct Memory Access) Line of signal
IRQx: Cut off the signal line of request.
DRQx: DMA asks for the line of signal.
DACKx#: DMA answer signal line.
1. 2 address spaces
PC/ AT system uses different orders to visit space of memory and IO end me: A space, PC/ 104 bus drives MEMR # and MEMW # signal while visiting the space of memory, PC/ 104 bus drives IOR # and IOW # signal while visiting the space of memory. Two spaces use the same set of address thread, but because there is effective 64K only in the port space, so pay IO port while visiting there is only SA on the line in the address <15:O> .
PC/ AT system have special port visit order, use for, realize port visit, procedure, user of Linux, need, transfer ioperm so as to root authority only ‘) The appointed port address range that needs to operate, later can visit these ports freely. Visit the order because of a group of great ports that corresponds to CPU directly in fact that are used for visiting the port, so it is very efficient to deposit and withdraw.
1. 3 PC/ 104 bus cycle
104 of PC/ bus cycle divide into by CPU and drive and last two big class DMA controller,at reading frequently used in not employings embedded /IO last cycle.
Adopt 104 bus Rd of standard PC/ of 8 MHz clock and is greater than 300 ns in Fig. 1, tAF should be greater than 250 ns, tRDpw is about 500 ns.
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